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DC removal algorithm now with latency

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Silas Oettinghaus
2023-10-12 16:43:54 +02:00
parent 0452d34f67
commit 025498d120
3 changed files with 169 additions and 140 deletions
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41
Classes/04_DSP/EQ_silas.m
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@@ -33,7 +33,6 @@ classdef EQ_silas < handle
e_ffe
e_dfe
e_dc
error_log
% coefficients
mu_dc_train
@@ -52,8 +51,8 @@ classdef EQ_silas < handle
trainloops
ddloops
dcmode
eq_blocklength % block lengt of EQ (until now, only the dc subtraction is affected by this)
eq_updatelatency % time in symbols until the calculated updates reach the signal again (until now, only the dc subtraction is affected by this)
@@ -80,7 +79,8 @@ classdef EQ_silas < handle
options.mu_ffe_dd = [0.0004 0.0005 0.0006];
options.mu_dfe_dd = 0.0005;
options.dcmode = 1;
options.eq_blocklength = 1;
options.eq_updatelatency = 1;
end
fn = fieldnames(options);
@@ -106,7 +106,7 @@ classdef EQ_silas < handle
end
function [signalclass_out,error_log] = process(obj,signalclass_in, reference_signalclass_in)
function [signalclass_out] = process(obj,signalclass_in, reference_signalclass_in)
% actual processing of the signal (steps 1. - 3.)
% 1 normalize RMS
@@ -151,12 +151,15 @@ classdef EQ_silas < handle
%% Adaptive Equalization Modes
function trainingMode(obj)
dc_block = ones(obj.eq_blocklength,1);
for tloop = 1:obj.trainloops
m = 1+obj.delay;
dc_cnt = 0;
for n = obj.sps*obj.delay+1:obj.sps:obj.sps*obj.trainlength
m = m+1;
dc_cnt = dc_cnt+1;
%get Sigal input vectors with correct length for VNLE
x_in_block = obj.x_in(obj.Ne(1)+n+(obj.sps-1):-1:n+obj.sps).';
@@ -173,9 +176,7 @@ classdef EQ_silas < handle
% Calculate the Error
obj.error = obj.e_dc + obj.e_ffe - obj.e_dfe - obj.d(obj.Nb(1)-1+m-obj.delay);
err_track(n) = obj.error;
if obj.mu_ffe_train ~= 0
%update FFE coefficients with LMS
@@ -189,7 +190,12 @@ classdef EQ_silas < handle
obj.b = obj.b + obj.mu_dfe_train*obj.error*d_vnle_format;
%update DC error
obj.e_dc = obj.e_dc - obj.error .* obj.mu_dc_train;
dc_block(dc_cnt) = obj.error .* obj.mu_dc_train;
if dc_cnt == obj.eq_blocklength
obj.e_dc = obj.e_dc - mean(dc_block(dc_cnt));
dc_cnt = 0;
end
end
@@ -203,10 +209,12 @@ classdef EQ_silas < handle
%start the dd mode with coefficients from training
coeff = [obj.e;obj.b];
dc_block = ones(obj.eq_blocklength,1);
for ddloop = 1:obj.ddloops
m = 0;
dc_cnt = 0;
mu_mat = diag([ones(1,obj.Ce(1))*obj.mu_ffe_dd(1)... %1st order ffe
ones(1,obj.Ce(2))*obj.mu_ffe_dd(2)... %2nd order ffe
@@ -226,7 +234,7 @@ classdef EQ_silas < handle
d_hat = zeros(obj.x_length,1);
for k = 1:obj.sps:obj.x_length
dc_cnt = dc_cnt+1;
m=m+1;
%get Sigal input vectors with correct length for VNLE
@@ -254,9 +262,14 @@ classdef EQ_silas < handle
coeff = coeff - mu_mat*obj.error*conj(x_d);
obj.e_dc = obj.e_dc - obj.mu_dc_dd * obj.error;
%update DC error
dc_block(dc_cnt) = obj.error .* obj.mu_dc_dd;
obj.error_log(ddloop,m) = obj.e_dc.^2;
if dc_cnt == obj.eq_blocklength
obj.e_dc = obj.e_dc - mean(dc_block(dc_cnt));
dc_cnt = 0;
end
% Append new decision to decision feedback
if obj.Nb(1) > 0