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Minor changes from lab pc

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Silas Labor Zizou
2025-04-08 13:29:12 +02:00
parent 8c49ec62e0
commit f93d61f5d8
5 changed files with 78 additions and 23 deletions
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12
Classes/05_Lab/AwgKeysight.m
View File

@@ -220,10 +220,10 @@ classdef AwgKeysight
v = visadev('TCPIP0::zizou.tf.uni-kiel.de::hislip0::INSTR');
case awg_model.M8199B
v = visadev('TCPIP0::localhost::hislip0::INSTR');
case awg_model.M8199A
v = visadev('TCPIP0::Zizou::hislip2::INSTR');
case awg_model.M8199A_ILV
v = visadev('TCPIP0::Zizou::hislip0::INSTR');
case awg_model.M8199A_ILV
v = visadev('TCPIP0::Zizou::hislip0::INSTR');
v = visadev('TCPIP0::Zizou::hislip2::INSTR');
end
debug = 0;
@@ -327,13 +327,13 @@ classdef AwgKeysight
elseif obj.model == awg_model.M8199B || obj.model == awg_model.M8199A || obj.model == awg_model.M8199A_ILV
% SET Ref clock out (which is conn. to scope) to 10 MHz
obj.writeNcheck(v, ':OUTPut:FREQuency ''M1.RefClkOut'',10000000');
% SET Ref clock out (which is conn. to scope) to 100 MHz
obj.writeNcheck(v, ':OUTPut:FREQuency ''M1.RefClkOut'',100000000');
% :OUTP:GLOB 'M1.System', OFF
obj.writeNcheck(v, ':OUTP:GLOB ''M1.System'', ON');
obj.writeNcheck(v, ':OUTP:GLOB ''M2.System'', ON');
%obj.writeNcheck(v,':INIT:IMMediate ''M2''');
obj.writeNcheck(v,':INIT:IMMediate ''M2''');
end
% operation ceomplete (opc)

2
Classes/05_Lab/OptAtten.m
View File

@@ -276,7 +276,7 @@ classdef OptAtten < handle
cnt = cnt+1;
end
fprintf("\n SET: CH1 %.2f dB | CH2: %.2f dB | CH3: %.2f dB | CH4: %.2f dB\n",obj.value_state(1), obj.value_state(2), obj.value_state(3), obj.value_state(4));
fprintf("\n Pset: CH1 %.2f dB | CH2: %.2f dB | CH3: %.2f dB | CH4: %.2f dB\n",obj.value_state(1), obj.value_state(2), obj.value_state(3), obj.value_state(4));
fprintf(" ATT: CH1 %.2f dB | CH2: %.2f dB | CH3: %.2f dB | CH4: %.2f dB\n",obj.atten_state(1), obj.atten_state(2), obj.atten_state(3), obj.atten_state(4));
fprintf(" POW: CH1 %.2f dBm | CH2: %.2f dBm | CH3: %.2f dBm | CH4: %.2f dBm \n \n",obj.power_state(1), obj.power_state(2), obj.power_state(3), obj.power_state(4));