22 lines
432 B
Verilog
22 lines
432 B
Verilog
/* Sample Verilog code, which doesn't really do anything
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* but it does show syntax highlighting
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*/
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module main(inputVar, flip);
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input inputVar;
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input flip;
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reg flop;
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// Comment about dummy code which doesn't work
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always @(posedge flip or posedge inputVar)
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if (reset)
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begin
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flop <= (0 & ~inputVar);
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end
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else
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begin
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$display("Hello world!");
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$finish;
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end
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endmodule
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