silas (home) 5c39a7f98a new minimal example ...

new project: FSO stuff

2026-01-07 15:07:38 +01:00

..

imdd_example_live.mlx

Many changes for 400G DSP

2024-12-17 16:17:58 +01:00

imdd_it.m

new minimal example

2026-01-07 15:07:38 +01:00

imdd_model.m

new minimal example

2026-01-07 15:07:38 +01:00

minimal_example.m

new minimal example

2026-01-07 15:07:38 +01:00

model_linewidth_evaluation.m

ML_MLSE (before testing in depth)

2025-10-31 10:36:13 +01:00

parameters.m

Many changes for 400G DSP

2024-12-17 16:17:58 +01:00

rx_simulation.m

Many changes for 400G DSP

2024-12-17 16:17:58 +01:00

simulation_bwl_2.m

new chirped modulator with alpha setting

2026-01-05 14:54:05 +01:00

simulation_bwl.m

ML_MLSE (before testing in depth)

2025-10-31 10:36:13 +01:00

submit_handle.m

few changes in WDM stuff

2026-01-07 08:30:14 +01:00

submit_simulations.m

Many changes

2025-02-14 14:54:03 +01:00

tx_simulation.m

Many changes towards simulation of JLT and once again the evaluation of the Highspeed data from Lab experiments 2024

2025-07-09 10:50:53 +02:00